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Prof. S. Yamamoto
Assoc. Prof. H.Takizawa

Computer Architecture

Japanese version

Lab's Web page
  Our laboratory is active in the research and education of high-performance, low-power, and dependable computer system architectures as below.

(1) Programming Models and Supportive Tools
  It is necessary to well understand and exploit the parallelism of the underlying hardware for high performance. We are developing programming models and supportive tools to facilitate the parallel programming and code optimization.

(2) Highly-efficient and Dependable Computing
  HPC systems are becoming larger and more complicated, so hardware/software failure problems become severe. We are exploring management mechanisms to make a massively parallel computing system more efficient and more dependable.

(3) Hardware/Software Co-design for Domain Specific Applications
  Hardware design needs to consider the performance characteristics of the target applications and application domains to improve power efficiency. We are researching hardware/software co-design for domain specific applications to achieve both high-performance and low power consumption.

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Fig. 1 Technologies for appointing the right processor to the right task.

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Fig. 2 Checkpoint-restart for resisting system failures.

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